S25FL128SAGNFV001

S25FL128SAGNFV001 is an SPI multi-I/O, 3.0V FL-S flash memory. It connects to a host system via a SPI. Traditional SPI single-bit serial input and output (Single I/O or SIO) is supported as well as optional two-bit (Dual I/O or DIO) and four-bit (Quad I/O or QIO) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erasing than prior generation SPI programs or erase algorithms. It offers high densities coupled with the flexibility and fast performance required by a variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.

• 128Mb density, 65nm MIRRORBIT™ process technology, 133MHz speed
• CMOS 3.0V core with versatile I/O, SPI clock polarity and phase modes 0 and 3
• Multi I/O command set and footprint compatible with S25FL-P SPI family
• Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR
• AutoBoot-power up or reset and execute Normal or Quad read command automatically at preselected addr
• Common flash interface (CFI) data for configuration information
• Quad-input page programming (QPP) for slow clock systems
• Automatic ECC-internal hardware error correction code generation with single bit error correction
• 100,000 program-erase cycles, minimum
• 8-contact WSON 6 x 8 mm package, industrial plus temperature range from -40°C to + 105°C