A3P125-TQG144

A3P125-TQG144 ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low power, single-chip solution that is instant on. ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P125 device has no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM Cortex-M1 processor.

• 125,000 system gates
• Thin quad flat pack (0.019inch pitch)
• Commercial application (temperature range) (0°C to +85°C junction temperature)
• 1,024 typical equivalent macrocells
• 96 maximum user I/Os, 2 I/O banks, secure (AES) ISP
• 1Kbits FlashROM, 36Kbits RAM (1,024 bits)
• ARM processor support in ProASIC3 FPGAs
• Segmented, hierarchical routing and clock structure
• Core voltage for low power, support for 1.5V-only systems, low impedance flash switches
• IEEE 1149.1 (JTAG) boundary scan test, pin-compatible packages across the ProASIC3 family

Notes

Device does not include license to implement IP based on the cryptography research, Inc. (CRI) patent portfolio.