Meet the AMD Spartan™ UltraScale+™ FPGA
High I/O, Low Power, State-of-the-art Security Features
Meet the AMD Spartan™ UltraScale+™ FPGA
Built on AMD UltraScale™ architecture and optimized for cost-sensitive applications requiring high I/O count, low power, and state-of-the-art security features
The AMD Spartan™ UltraScale+™ FPGA family helps designers with their growing need for secure devices that can handle large amounts of data. With more devices and sensors connected at the edge, Spartan UltraScale+ FPGAs help designers rapidly move through challenges by delivering low cost, power efficiency, and modern security features. With densities ranging from 11K to 218K logic cells and up to 572 I/Os, Spartan UltraScale+ FPGAs excel in a wide range of use cases, from I/O expansion and board management to sensor processing and control.
Whether it be machine vision, industrial, healthcare, data center, or broadcasting, the versatility and efficiency provided by Spartan UltraScale+ FPGAs provide robust solutions for a broad array of applications. Developers can benefit from the AMD UltraScale™ architecture, allowing for scalability to other 16 nm families, as well as the broader portfolio. Equipped with high-speed transceivers, substantial built-in and external memory, and PCIe® Gen4, Spartan UltraScale+ FPGAs offer a proven solution for your next project.
Applications
Industrial and Edge
Factory Automation and Robotics | IIoT Gateways and Edge Appliances | Smart City and Smart Grid
Healthcare and Sciences
Medical Equipment | Imaging (Ultrasound, CT/MRI, Endoscopy)
Wired and Wireless
Wireless Infrastructure | Access Network and Connectivity
Data Center and Cloud
Storage Acceleration | Data Center Interconnect
Pro AV and Broadcast
PCIe Video Cards | Video Converters and AV-over-IP
Features and Benefits
High I/O, low-power FPGAs with state-of-the-art security features
- Highest I/O-to-logic-cell ratio1 in the AMD Cost-Optimized Portfolio (COP)
- Interface flexibility with 1.2V to 3.3V I/O, 16.3 Gb/s transceivers
- Simplified connectivity PCIe® Gen4, MIPI D-PHY, and LPDDR4X/5
- Up to 30% power reduction2 with 16 nm FinFET & power efficiency through hard DDRMC and PCIe IP
- Advanced security features to protect your IP, prevent tampering, and maximise uptime
Get to market fast with proven AMD Vivado™ tools
- Maximise development efficiency with end-to-end IDE spanning synthesis, place and route, simulation, and debug
- Minimise onboarding with single IDE for broad portfolio: 28 nm, 20 nm, 16 nm, and 7 nm
Design once with a trusted supplier
- Nearly four decades of industry experience
- Support 15+ years of product lifecycle
- Worldwide Distribution, Sales, and Support
1 Based on AMD internal analysis December 2023, comparing the total I/O-to-logic-cell ratio for AMD Spartan™ UltraScale+™ FPGAs to previous generations of AMD cost-optimized FPGAs. (SUS-001)
2 Projection is based on AMD labs internal analysis in January 2024, using total power calculation (static plus dynamic power) based on the difference in logic cell count of an AMD Artix™ UltraScale+™ AU7P FPGA, to estimate the power of a 16 nm AMD Spartan™ UltraScale+™ SU35P FPGA versus a 28 nm AMD Artix™ 7 7A35T FPGA, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Total power estimates and projections will vary when products are released in market and based on design, configuration, usage, and other factors. (SUS-003)
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