S25FS256TDACHC113

S25FS256TDACHC113 is a S25FS256T 256Mb SEMPER™ nano flash memory. This device is CMOS, MIRRORBIT™ NOR flash device that supports traditional SPI single-bit serial input and output, as well as four-bit wide quad output protocols. Read transactions use a linear burst reading the whole memory array. The erased state of each memory bit is logic 1. Programming changes logic 1 (HIGH) to logic 0 (LOW). Only an erase operation can change a memory bit from a 0 to a 1. An erase operation must be performed on a complete sector (64KBs or 128KBs).

• Configurable sector architecture options for 128KB (2bpc) and 64KB (1bpc) sectors
• Interface, SPI, supports 1S-1S-1S protocols, 80MHz SDR speed
• Hardware reset through CS# signaling method (JEDEC) or individual RESET# pin
• Ready busy (RD/BY# = LOW) indicates that an internal event is ongoing
• Device identification, manufacturer identification, and unique identification
• Data retention, 1bpc sector end of life minimum 0.28 year retention
• Supply voltage range from 1.7V to 2.0V
• Page programming buffer of 256 or 512 bytes, OTP secure silicon array of 1024 bytes (32 x 32 bytes)
• WLCSP package
• Commercial temperature range from 0°C to +70°C