S25FL128LAGMFB013

S25FL128LAGMFB013 is a S25FL128L series non-volatile SPI flash memory IC using floating gate technology and 65nm process lithography. The FL-L family connects to a host system via a serial peripheral interface (SPI). The architecture features a page programming buffer that allows up to 256bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using this at the higher clock rates supported, with quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically. This offers high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections and power. This is ideal for code shadowing to RAM, executing code directly (XIP), and storing re-programmable data.

• Clock polarity and phase modes 0 and 3, read modes: burst wrap, continuous (XIP), QPI
• Serial flash discoverable parameters (SFDP) for configuration information
• Erase architecture uniform 4KB sector erase, uniform 32KB half block erase, uniform 64KB block erase
• 100000 program/erase cycles minimum, 20 year data retention minimum
• Four security regions of 256bytes each outside the main flash array
• Status and configuration register protection, individual and region protection
• Individual block lock: volatile individual sector/block, pointer region
• Single supply voltage with CMOS I/O 2.7V to 3.6V
• 128Mb density, 133MHz speed, SOIC package
• Automotive, AEC-Q100 grade 2 (–40 to 105°C) temperature, SOIC8 (208 Mil) / 8-contact WSON footprint