S25FL512SAGMFI013

S25FL512SAGMFI013 is a FL-S flash non-volatile memory. It uses MirrorBit™ technology - that stores two data bits in each memory array transistor and eclipse architecture - that dramatically improves program and erase performance. This device connects to a host system via an SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.

• 512Mb density, 65nm mirrorbit process technology, 133MHz speed
• CMOS 3.0V core with versatile I/O, SPI with multi-I/O
• SPI clock polarity and phase modes 0 and 3
• Multi I/O command set and footprint compatible with the S25FL-P SPI family
• Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR READ commands
• Common Flash Interface (CFI) data for configuration information
• Quad-input page programming (QPP) for slow clock systems
• 100000 minimum program-erase cycling endurance
• Status register bits to control protection against program or erase of a contiguous range of sectors
• 16-pin SO package, industrial temperature range from -40°C to + 85°C