MT46V32M16CY-5B IT:J

MT46V32M16CY-5B IT:J is a double data rate (DDR) SDRAM. The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The DDR SDRAM provides programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#), commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK, four internal banks for concurrent operation
• Auto refresh – 64ms, 8192-cycle
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL-2 compatible), concurrent auto precharge option is supported
• 32 Meg x 16 configuration, timing – cycle time: 5ns at CL = 3 (DDR400)
• FBGA package
• Industrial temperature range from -40°C to 85°C