IS43TR16512BL-107MBL

IS43TR16512BL-107MBL is a 512Mx16 1866MT/s 8Gb DDR3 SDRAM. The memory controller initiates Levelling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write levelling mode, the DQ pins are in undefined driving mode. During write levelling mode, only NOP or DESELECT commands are allowed, as well as an MRS command to exit write levelling mode. Since the controller levels one rank at a time, the output of other ranks must be disabled by setting MR1 bit A12 to 1. DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on the DQ bus asynchronously after tWLO timing. In this product, all data bits ("prime DQ bit(s)") which are DQ0~DQ7 for x8, or DQ0~DQ15 for x16, provide the levelling feedback.

• Standard voltage is VDD and VDDQ = 1.5V ± 0.075V
• High-speed data transfer rates with system frequency up to 933MHz
• 8 internal banks for concurrent operation, 8n-bit pre-fetch architecture
• Programmable CAS latency, programmable additive latency: 0, CL-1, CL-2
• Programmable CAS WRITE latency (CWL) based on tCK, BL switch on the fly, auto self refresh (ASR)
• Programmable burst sequence: sequential or interleave, self refresh temperature (SRT)
• Partial array self refresh, asynchronous RESET pin, write levelling
• OCD (off-chip driver impedance adjustment), dynamic ODT (on-die termination)
• 96-ball BGA package
• Industrial temperature rating range from -40°C ≤ TC ≤ 95°C