AS4C512M16MD4V-053BIN

AS4C512M16MD4V-053BIN is a LPDDR4x SDRAM. It is a high-speed synchronous DRAM device internally configured with either 1 or 2 channels. This device uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 16n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR4X SDRAM effectively consists of a single 16n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the devices are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

• 8Gb (512Mx16) memory organization, 1866MHz maximum clock frequency
• Double-data rate architecture; two data transfers per clock cycle
• Auto precharge option for each burst access, configurable drive strength
• Refresh and self refresh modes, partial array self refresh and temperature compensated self refresh
• Write levelling, CA calibration, internal VREF and VREF training, FIFO based write/read training
• MPC (multi purpose command), LVSTLE (low voltage swing terminated logic extension) IO
• Edge aligned data output, write training for data input center align, refresh rate is 3.9us
• Clock period jitter is 40ps maximum, input slew rate over VcIVW is 7V/ns maximum
• Industrial operating temperature range from -40°C to 85°C, LVSTLE-06 interface
• 200-ball FBGA package