MTA9ASF1G72HZ-3G2R1

MTA9ASF1G72HZ-3G2R1 is a high-speed DDR4 SDRAM module. DDR4 SDRAM module benefits from the DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.

• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR), data bus inversion (DBI) for data bus
• On-die VREFDQ generation and calibration, single-rank, 16 internal banks, 4 groups of 4 banks each
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF), gold edge contacts, fly-by topology
• Terminated control, command, and address bus
• 8GB module density, 1 Gig x 72 configuration, 25.6GB/s module bandwidth
• 260-pin DIMM package, 0°C ≤ TOPER ≤ 95°C commercial operating temperature