MT28FW02GBBA1HPC-0AAT

MT28FW02GBBA1HPC-0AAT is an asynchronous, uniform block, parallel NOR flash memory device. It is a 2Gb stacked device that contains two 1Gb dies. It is selected by the A[max]. While A[max] = 0, the lower 1Gb die is selected, and while A[max] = 1, the upper 1Gb die is selected. READ, ERASE, and PROGRAM operations are performed using a single low voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. Command set required to control the device is consistent with JEDEC standards.

• Voltage range from 2.7 to 3.6V core, 1.7 to 3.6V I/O
• 2Gb density, dual die stack, x16 configuration, high lock block structure
• 2Gb stacked device (two 1Gb die), single-level cell (SLC) process technology
• Word program is 25µs per word (TYP), block erase (128KB) is 0.2s (TYP)
• Read from another block during a PROGRAM SUSPEND operation
• Read or program another block during an ERASE SUSPEND operation
• Unlock bypass, block erase, die erase, and write to buffer capability
• BLANK CHECK operation to verify an erased block
• CYCLIC REDUNDANCY CHECK (CRC) operation to verify a program pattern
• 64-ball LBGA package, operating temperature range from -40 to +105°C (Grade 2 AEC-Q100)