MT41K256M16TW-107:P

MT41K256M16TW-107:P is a DDR3L SDRAM (1.35V). The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK.

• 256 Meg x 16 configuration, tCK = 1.07ns, CL = 13 speed grade, 1866MT/s data rate
• 13-13-13 target tRCD-tRP-CL, 13.91ns tRCD, 13.91ns tRP, 13.91ns CL, 8K refresh count
• 32K (A[14:0]) row address, 8 (BA[2:0]) bank address, 1K (A[9:0]) column address, 2KB page size
• VDD = VDDQ = 1.35V (1.283 to 1.45V), backward compatible to VDD = VDDQ = 1.5V ±0.075V
• Supports DDR3L devices to be backward compatible in 1.5V applications
• Differential bidirectional data strobe, 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#), 8 internal banks, self refresh mode
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS latency, programmable posted CAS additive latency, programmable CAS latency
• 96 ball FBGA package, commercial operating temperature range from 0 to 95°C